Negative bias temperature instability is the tendency of a p-type metal oxide semiconductor (PMOS) transistor to degrade in performance when its gate terminal is biased negatively relative to the remaining terminals of the transistor over time. Negative bias temperature instability can increase the required threshold voltage of the transistor gate and decrease the drive current of the transistor. As a result, this instability has become one of the dominant reliability concerns in advanced complementary metal oxide semiconductor (CMOS) processes. Characterizing the effects of negative bias temperature instability on a given model of transistor is thus important in predicting an operational lifetime for the transistor and the products in which it is utilized.
One methodology for characterizing a negative bias temperature instability associated with a transistor includes connecting the source, drain, and body terminals of the transistor to ground. A stress voltage exceeding the normal operating voltage (in magnitude) of the transistor is then applied to the gate terminal of the transistor for a desired period. The stress voltage is removed from the gate terminal after a desired period. To measure the effects of the applied stress, a bias voltage (typically the operating voltage) is applied to the drain terminal and the current produced across the transistor by the bias voltage is measured. The bias voltage is then removed and the stress is reapplied. This cycle repeats until a desired number of cycles are completed.
A problem associated with the described methodology is that during measurements, the stress voltage to the gate is discontinued for a short time for each drain current measurement. During this time, an annealing effect associated with the transistor produces a significant recovery in the characteristics of the transistor, effectively reversing the degradation by a small amount. This recovery provides a source of error in characterizing the instability produced in the transistor. Further, the length of the delay is not standard between various testing methods, making it difficult to compare results obtained by different methods.